Texas Instruments /MSP432P401M /DWT /DWT_CTRL

Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0.

Reload value for POSTCNT, bits [8:5], post-scalar counter. If this value is 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change.

Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]).

Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]. When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.

0 (en_0b0): selects bit [6] to tap

1 (en_0b1): selects bit [10] to tap.

Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1.

0 (en_0b00): Disabled. No synch counting.

1 (en_0b01): Tap at CYCCNT bit 24.

2 (en_0b10): Tap at CYCCNT bit 26.

3 (en_0b11): Tap at CYCCNT bit 28.

Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]). Reset clears the PCSAMPLENA bit.

0 (en_0b0): PC Sampling event disabled.

1 (en_0b1): Sampling event enabled.

Enables Interrupt event tracing. Reset clears the EXCEVTENA bit.

0 (en_0b0): interrupt event trace disabled.

1 (en_0b1): interrupt event trace enabled.

Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions). Reset clears the CPIEVTENA bit.

0 (en_0b0): CPI counter events disabled.

1 (en_0b1): CPI counter events enabled.

Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). Reset clears the EXCEVTENA bit.

0 (en_0b0): Interrupt overhead event disabled.

1 (en_0b1): Interrupt overhead event enabled.

Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit.

0 (en_0b0): Sleep count events disabled.

1 (en_0b1): Sleep count events enabled.

Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. Reset clears the LSUEVTENA bit.

0 (en_0b0): LSU count events disabled.

1 (en_0b1): LSU count events enabled.

Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. Reset clears the FOLDEVTENA bit.

0 (en_0b0): Folded instruction count events disabled.

1 (en_0b1): Folded instruction count events enabled.

Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit.

0 (en_0b0): Cycle count events disabled.

1 (en_0b1): Cycle count events enabled.

When set, DWT_FOLDCNT, DWT_LSUCNT, DWT_SLEEPCNT, DWT_EXCCNT, and DWT_CPICNT are not supported.

When set, DWT_CYCCNT is not supported.